1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having a floating gate type memory element.
2. Description of the Background Art
FIG. 11 is a circuit diagram showing a circuit configuration of a memory cell array in a non-volatile semiconductor memory device such as a conventional flash memory. In FIG. 11, there is shown, as one example, a circuit configuration of a memory cell array in a NOR type flash memory.
Referring to FIG. 11, so-called floating gate type memory cell transistors are arranged in a matrix and word lines WLm−1 to WLm+1 and bit lines BLn−1 to BLn+1 (m,n: a natural number) are arranged in row and column directions, respectively. The drain, source and gate of each memory cell transistor is connected to a bit line, a source line and a word line, respectively. For the figure, description will be given of a memory cell transistor MT (m, n) encircled with a dotted line as an example and the drain of the memory cell transistor MT (m, n) is connected to a bit line BLn and the source thereof is connected to a source line SL common to memory cell transistors and the gate thereof is connected to a word line WLm.
FIG. 12 is a sectional view schematically showing a structure of a floating gate type memory cell transistor.
Referring to FIG. 12, a drain region D and a source region S are formed on a main surface of a semiconductor substrate SUB. A floating gate F is formed in a layer above a channel region between drain region D and source region S with an insulating film interposed between itself and the channel region, and a control gate G is formed on a layer further thereabove with an insulating film interposed therebetween. A drain voltage Vd, a source voltage Vs, a control gate voltage Vcg and a substrate voltage Vsub are applied to drain region D, source region S control gate G and semiconductor substrate SUB, respectively.
Description will be given of data writing with channel hot electrons (hereinafter, referred to as “CHE”) in a floating gate type memory cell transistor.
FIG. 13 is a table showing a general voltage arrangement in data writing with CHE in the floating gate type memory cell transistor shown in FIG. 12. In the table, voltage “in program” corresponds to a voltage arrangement in data writing.
Referring to FIGS. 12 and 13, when drain voltage Vd of 4 to 5 V is given, a high electric field region is formed in the vicinity of drain region D. Electrons flowing in a channel region from source region S toward drain region D are driven into an high energy state in this high electric field region. CHE whose energy is raised to a value equal to or higher than 3.8 eV, which is a potential barrier φb at an oxide insulating film interface between the channel region and floating gate F, are attracted toward floating gate F under an electric field generated by control gate voltage Vcg applied to control gate G and injected into floating gate F.
Unless electrons have not been accumulated in floating gate F prior to the injection of CHE, the potential of floating gate F at an initial stage of the injection takes a potential determined by αcg×Vcg. Here, αcg is a capacitive coupling coefficient and generally on the order of 0.7. Therefore, when control gate voltage Vcg is 10 V, potential of floating gate F takes a value of the order of 7 V and, under the potential, CHE are attracted and injected into floating gate F. A state in which CHE have been injected into floating gate F is called “a program state,” which corresponds to a state where data “0” is stored. On the other hand, a state where no CHE has been injected into floating gate F is called an “erase state,” which corresponds to a state where data “1” is stored.
Data reading is performed as follows. In a program state, by injecting electrons into floating gate F, a threshold voltage Vth of a memory cell transistor rises relative to control gate G. Therefore, as shown in FIG. 13, even if drain voltage Vd of the order of 1 V is given and a voltage of 5 V is given to control gate voltage Vcg, a memory cell transistor is not turned on and no channel current flows. On the other hand, in an erase state, by applying a voltage of 5 V higher than a threshold voltage in the erase state to control gate Vcg, the memory cell transistor is turned on.
Therefore, when drain voltage Vd of the order of 1 V is applied and a voltage of 5 V is applied as control gate voltage Vcg, reading of storage data is determined by whether or not a current flows in a memory cell transistor.
A storage state where electrons have been once injected into the floating gate is held in the floating gate till an erase pulse is applied, and since no electron injection into a floating gate is performed as far as a prescribed voltage for program is not applied, an electron state in the floating gate is held even if a device power supply is tuned off. That is, a non-volatile memory is thus realized.
In a flash memory, a strong demand for a single power supply has been built up in recent years and in order to satisfy such a demand, generally a charge pump circuit is provided inside a device. That is, only a desired single power supply (3.3 V, 2.5 V or the like) is supplied externally to a logic circuit system inside the device and a voltage higher than the above single power supply voltage, which is required in data writing to a memory cell transistor or in erasure therein described later, is generated by a charge pump circuit.
The charge pump circuit is required to be used within a range not exceeding a current drive ability of the charge pump circuit in order to stably generate a desired boosted voltage. The current drive ability of a charge pump circuit is generally proportional to an area of the charge pump circuit.
In a case where data is written by injecting CHE into a floating gate, a current of the order from 150 to 200 μA flows in one memory cell transistor for an instant at an initial stage of the writing. In order to reduce a data write time, in a NOR type flash memory, simultaneous data writing is generally performed to 8 bits or 16 bits (that is 8 or 16 memory cell transistors). Therefore, in this case, a charge pump circuit needs a current drive ability of the order of 200 μA×16 bits=3.2 mA at an initial stage of a write operation. When the charge pump circuit cannot drive this amount of current, a desired boosted voltage is not given to the memory cell transistor with the result of occurrence of a write operation fault.
A change toward a low voltage given to a device has increasingly progressed: such as from 3.3 V to 2.5 V and further 1.8 V, in these several years and, along with the state, a required current drive ability of a charge pump circuit has also increased, which, in turn, increases an occupancy area of the charge pump circuit on the device. From the viewpoint of a low cost, it is important to reduce an area of a charge pump circuit and to thereby decrease a size of a device and, in order to reduce an area of the charge pump circuit, it is necessary to suppress a current drive ability of the charge pump circuit by suppressing a channel current in CHE injection.
As methods suppressing a channel current, a method is described in U.S. Pat. No. 5659504. According to this method, by applying a negative bias of the order of −1 V to a semiconductor substrate, a channel current is suppressed by a substrate bias effect. Furthermore, by enhancing a potential difference between the gate and the substrate, electrons each having energy in the vicinity of a potential barrier at an insulating oxide film interface are attracted to a floating gate. As a result of the attraction, an injection efficiency of CHE rises while suppressing a channel current when CHE are injected, thereby enabling efficient writing.
On the other hand, while, in a flash memory, erasure of data is performed by extracting electrons having been injected into the floating gate, electrons at this time are excessively extracted from the floating gate by chance, a threshold voltage Vth of a memory cell transistor relative to the control gate enters a depletion state (Vth <0); a so-called over-erased state is generated.
FIGS. 14 to 16 are graphs showing transitions of distributing states of a threshold voltage Vth concerning a memory cell transistor on a memory cell array in erasure.
FIG. 14 is a graph showing a distribution of values of a threshold voltage prior to erasure.
Referring to FIG. 14, in a state prior to erasure, distributions of a threshold voltage is altered in two ways between a program state and an erasure state. Note that the ordinate of a graph used for plotting the number of memory cell transistors each holding a threshold voltage on a memory cell array.
FIG. 15 is a graph showing a distribution of a threshold voltage in the course of erasure. The erasure is performed by repetition of application of an erase pulse with a prescribed width to a memory cell transistor, and an erase verify determination to confirm a threshold voltage combined.
Referring to FIG. 15, by applying an erase pulse to memory cell transistors, a peak of a threshold voltage Vth shifts in a direction of a decrease in threshold voltage.
FIG. 16 is a graph showing a distribution of a threshold voltage Vth after erasure ends.
Referring to FIG. 16, since erase verify has been completed on all memory cell transistors, threshold voltages Vth of all the memory cell transistors are lower than an erase verify voltage 3.5 V. There arise considerable variations in threshold voltages of the memory cell transistors, however. As a result, it is shown with a hatched portion with oblique lines that there are memory cell transistors in a depletion state in which a threshold voltage Vth is 0 V or lower, that is in an ever-erased state.
In a memory cell transistor structure of a flash memory, especially, having an array structure called a NOR type or a DINOR (Divided bit line NOR) type, the presence of even a single memory cell transistor in an over-erased state disables correct measurement of threshold voltages Vth of all the other memory cell transistors on a bit line to which the memory cell transistor in an over-erased state. That is, no normal read operation can be performed on memory cell transistors connected to the bit line.
The reason for such an inconvenience is that, in FIG. 11, for example, in a case where memory cell transistor MT (m, n) is in a depletion state while threshold voltages Vth of other memory cell transistors on bit line BLn are even in an enhancement state (Vth >0), a current flows in memory cell transistor MT (m, n) when a voltage is applied to bit line BLn for measurement of threshold voltages of the other memory cell transistors even if no voltage is applied to word line WLn to which memory cell transistor MT (m, n) in a depletion state is connected.
As a measure to eliminate a problem of a memory cell transistor in an over-erased state, a self-selective write-back method with a drain avalanche gate current is reported by Yamada et al. in an article titled “A Self-Convergence Erase for NOR Flash EEPROM Using Avalanche Hot Carrier Injection”, appeared in IEEE Transactions on Electron Devices, Vol. 43, p. 1937–1941, 1996.
As another method to eliminate the problem of a memory cell transistor in an over-erased state, a self-selective write-back method using sub-threshold CHE has been proposed by the inventors of the present application.
The latter method enables injection of CHE into floating gate with a low drain voltage and performs writing-back using memory cell transistors with an enhanced injection efficiency of CHE. By using memory cell transistors according to this method, a voltage arrangement in a write-back operation shown in FIG. 13 is set and thereby a leak current of the order in the range of from 0.1 to tens of μA self-selectively flows in a memory cell transistor in an over-erased state.
FIG. 17 is a graph conceptually showing a gate voltage Vg dependency of a drain current of a single memory cell transistor.
Referring to FIG. 17, a threshold voltage is defined as a value of a control gate voltage Vg when a current value flowing in a memory cell transistor reaches a prescribed standard value Id—read. A curve C1 is a characteristic curve of a memory cell transistor when a threshold voltage Vth is at an erase verify level, that is the maximum threshold voltage max. Vth after erasure. A curve C2 is a characteristic curve of a memory cell transistor when a threshold voltage Vth is at a write-back verify level, that is at the minimum threshold value min. Vth after writing-back. A curve C3 is a characteristic curve of a memory cell transistor in an over-erased state.
When a voltage in a write-back operation shown in FIG. 13 is applied to a memory cell transistor to be erased, a leak current of the order in the range of from 0.1 to tens of μA per bit flows through a channel region in a memory cell transistor in an over-erased state as shown with the curve C3 in FIG. 13 even if control gate voltage Vg is 0 V. CHE are generated by this leak current itself in a high electric field region in the vicinity of the drain region and injected into the floating gate to thereby cause writing-back to be self-selectively performed in the memory cell transistor in an over-erased state.
FIG. 18 is a graph showing a manner in which a memory cell transistor in an over-erased state is written back over time.
Refreezing to FIG. 18, a threshold voltage Vth, as shown with the curve A, becomes asymptotic to 1.5 V in about 1 ms, which is a write-back verify level. Note that description will be given of the curve B later.
FIG. 19 is a graph showing a manner in which a memory cell transistor in an over-erased state has been written back and a distribution of a threshold voltage has been narrowed in width.
Referring to FIG. 19, self-selective writing-back is performed in a memory cell transistor corresponding to black circles, which were of low threshold voltage prior to writing-back to thereby raise the threshold voltages.
FIG. 20 is a flow chart for describing an erase sequence in writing-back using self-selective writing-back.
Referring to FIG. 20, an erase sequence starts (step S100) and when an input of an erase command is received from outside (step S102), a write operation prior to erasure is at first performed (step S104). Then, application of an erase pulse (step S106) and a erase verify determination (step S108) combined are repeated till a threshold voltage of a memory cell transistor with a maximum threshold voltage in a threshold voltage Vth distribution after erasure takes an erase verify level.
In succession, after an erase operation is completed (step S108), a write-back pulse is non-selectively applied to a bit line and a memory cell transistor in an over-erased state present on a bit line onto which a bit line potential is self-selectively written back (step S110). Then, the process ends when threshold voltages of all the memory cell transistors exceed a write-back verify level (step S112).
A trend to adopt a lower operating voltage by a device, as described above, has advanced in recent years and in company with this trend, an occupancy area of a charge pump circuit in a device has increased in order to secure a current drive ability of a charge pump circuit. Therefore, a great problem currently exists that an area of a charge pump circuit is reduced to in turn, decrease a size of a device.
It is in writing-back when an electron injection is singly performed on floating gates in each array or each prescribed block as a unit basis rather than in writing when electron injection into a floating gate of a selected memory cell transistor that a current drive ability of a charge pump circuit is problematic. Therefore, in order to reduce an area of a charge pump circuit, a necessity arises for suppressing a channel current in a write-back operation to thereby suppress a current drive ability of the charge pump circuit.
The method described in above U.S. Pat. No. 5,659,504 is a method associated with a write operation, wherein a channel current in CHE injection is suppressed while enhancing an injection efficiency of CHE, and which can also be applied in a write-back operation. According to the measure, however, a new negative potential of the order of −1 V has to be generated on a semiconductor substrate. Therefore, this method requires a voltage generating circuit generating a new negative substrate potential, though an occupancy area of a charge pump circuit generating drain voltage Vd can be reduced as a result of suppression of a channel current in CHE injection from the viewpoint of reduction in area of the charge pump circuit.
On the other hand, a self-selective write-back method using a drain avalanche gate current has strong points, of requiring no bit selection, and capable of performing writing-back self-convergently. Furthermore, since generation of potentials may be in almost the same setting as in a write operation, requirement arises for neither a circuit for selecting a memory cell transistor in an over-erased state nor a potential setting circuit for writing-back. Since a convergence current flows over the entire array, however, a drive current in a write-back operation is large and in addition, since electron injection and hole injection into a floating gate generates simultaneously, a problem arises that a channel conductance of a memory cell transistor is degraded.
The above prior art self-selective write-back method using sub-threshold CHE, similar to the self-selective write-back method using a drain avalanche gate current, has strong points, of requiring no bit selection, and capable of performing writing-back self-convergently. Generation of potentials may be in the same setting as in a write operation. Since a channel current is increasingly cutting off in state of writing-back, a drive current is progressively reducing as writing-back advances. Furthermore, since only electrons are injected into a floating gate, an advantage can be enjoyed that no channel conductance is degraded as compared with the above self-selective write-back method using drain avalanche gate current.
As pointed out in description of the above charge pump circuit, however, there remains a problem to increase a time till convergence is reached if reduction in voltage generates in single writing-back of each prescribed number of memory cell transistors as a unit basis from the viewpoint of a time required for writing-back and a circuit configuration. Note that this problem is true for the self-selective write-back method using a drain avalanche gate current.
Detailed description will be given of the problem below.
FIG. 21 is a graph conceptually describing a total of leak currents when a single writing-back is performed on a prescribed number of memory cell transistors with a self-selective write-back method.
Referring to FIG. 21, the abscissa is assigned to a threshold voltage of a memory cell transistor to be written back, while the ordinate is used for plotting a total of leak currents of the memory cell transistor.
When a writing-back is singly performed on a prescribed number of memory cell transistors by means of the self-selective write-back method, leak current has two current components. That is, one is a junction leak current flowing in all memory cell transistors and the other is a channel leak current flowing in a memory cell transistor in a low threshold voltage state. Here, the junction leak current is generated at a p-n junction, and depends on an applied bit line voltage but does not depend on a threshold voltage. The junction leak current is on the order of several nA as a maximum value per memory cell transistor. On the other hand, a channel leak current flows in a channel region between the source region and the drain region and an amount thereof increases at a lower threshold voltage. A channel leak current is on the order of 0.1 to tens of μA per memory cell transistor with a threshold voltage of 0 V.
In a case where a distribution of threshold voltages Vth of memory cell transistors to be written back is a high state, a junction leak current is dominant. On the other hand, a distribution of threshold voltages Vth is in a low state, a channel leak current is dominant in a total leak current. For example, a threshold voltage also varies by an influence of peripheral circuits from fluctuation in process parameters and thereby, if a threshold voltage Vth in an erased state is reduced to be lower or a distribution width of thresholds of memory cell transistors to be written back is broadened, a channel leak current increases.
As described above, a write-back operation is desirably performed collectively on a prescribed number of memory cell transistors from the viewpoint of time required for writing-back and a circuit configuration, memory cell transistors corresponding to the numbers of bits of 64 kB, generally, are subjected to a single writing-back. At this time, if a memory cell transistor is of a threshold voltage as low as 0.5 V or lower and a channel leak current of 1 μA on average flows therein, only a channel leak current of the order of 4 mA flows in total. On the other hand, a current drive ability of a charge pump circuit driving a bit line voltage is in most cases designed to be on the order of 3 mA based on a necessary ability in a write operation as described above; therefore a circuit area thereof would increase in order to cope with a current drive ability more than the value.
FIG. 22 is a graph showing a relationship between a total of leak currents in a write-back operation and an output voltage of a charge pump circuit.
Referring to FIG. 22, in a case where a current drive ability of a charge pump circuit is designed to be 3 mA, the charge pump circuit outputs a prescribed output voltage, as far as a total of leak currents does not exceed 3 mA of the upper limit of a current drive ability. On the other hand, if a total of leak currents exceeds 3 mA of the upper limit of a current drive ability, an output voltage of the charge pump circuit is on the decrease with a total of leak currents.
A decrease in output voltage of the charge pump circuit, that is a decrease in applied drain voltage hinders generation of a high electric field in the drain region of a memory cell transistor with the result that a generation efficiency of CHE is reduced, thereby making it difficult to produce sub-threshold CHE for eliminating an over-erased state.
That is, at an initial stage of writing-back, there are many of memory cell transistors each with a low threshold voltage and an increase in total leak current caused by channel leak currents in the memory cell transistors lowers an output voltage of a charge pump circuit. Therefore, in a conventional method, by the reduction in output voltage of a charge pump circuit, a time was consumed to eliminate a problem of a memory cell transistor in an over-erased state and in a worse case, a function of such an elimination of a problem itself more problematically does not work.
FIG. 23 is a graph showing an applied drain voltage dependency in convergence of a threshold voltage when writing-back using sub-threshold CHE is performed.
Referring FIG. 23, symbols of a white circle, a white triangle and a white square indicate respective cases where applied drain voltages are 4 V, 3 V and 2 V. It is found that as a drain voltage decreases, convergence of threshold voltages takes more of time.
Referring again to FIG. 18, a curve A is an ideal write-back convergence curve when a current drive ability of a charge pump circuit is sufficient, while a curve B is a write-back convergence curve when a current drive ability of a charge pump circuit is exceeded with respect to the upper limits. In such a way, in a conventional write-back method, there was a case where it actually takes time for a threshold voltage Vth to converge as shown in the curve B, dissimilar to the ideal write-back curve A, causing a write-back fault to be generated in some case.